Hardware validated · M.E. thesis
Layer-2 Ethernet security firewall
Moving Ethernet security policy into programmable logic, with a compact rule engine and bounded evaluation latency.
Explore projectEngineering portfolio
Engineering work.
Projects & contributions.
My work spans FPGA and RTL design, hardware security, verification, motor control and system architecture. Explore project case studies, reusable digital modules and engineering contributions.
Showing all 18 projects and contributions
Project case studies
Industry internship · Aviat Networks
Ethernet processing on Kria KR260
An industry internship exploring VLAN switching on a Zynq UltraScale+ SoC platform.
Explore projectSimulation · SystemVerilog / UVM
AXI4 master verification environment
Separating stimulus, observation, checking, and coverage to make protocol behaviour easier to verify.
Explore projectImplemented · Engineering practice
Engineering knowledge & design process
Making technical information easier to navigate, maintain, and use across a design programme.
Explore projectEngineering studies
RTL design, implementation analysis and simulation studies across digital systems and semiconductor devices.
Hardware network security
FPGA streaming entropy monitor
Developed an FPGA-side streaming entropy monitor with AXI data and control interfaces, evaluated in cycle-accurate RTL simulation. Co-authored the associated IEEE publication.
Related publicationRTL & IP development
AXI4-Lite LFSR custom IP
Developed an 8-bit linear-feedback shift register as a custom RTL IP block with an AXI4-Lite interface.
Digital design evaluation
FIR filter PPA characterisation
Studied FIR filter implementations through power, performance and area characterisation.
Semiconductor device simulation
Schottky diode TCAD study
Investigated Schottky-diode behaviour through technology computer-aided design simulations.
Industry contributions
Zepto Logic Technologies Pvt. Ltd. · Technical direction, engineering coordination and programme development.
Cryptographic accelerators
Zero-knowledge proof hardware acceleration
Technical review, validation planning, integration follow-up and release coordination within an established proof-acceleration programme.
Real-time simulation
EV inverter hardware-in-the-loop modelling
Technical direction, architecture review and milestone tracking for an FPGA-oriented inverter simulation platform.
Architecture & system design
Architecture, specifications and proposal development for cryptographic hardware, sensor interfaces and connected systems.
Cryptographic hardware architecture
Configurable cryptographic arithmetic accelerator
Architecture definition and technical planning for reusable modular-arithmetic hardware serving cryptographic workloads.
Sensor acquisition · Independent project
Configurable multi-protocol sensor interface IP
Architecture and specification for reusable sensor-acquisition RTL IP, bringing multiple digital interfaces and hardware event notification into a configurable design.
Industrial connectivity & embedded systems
Secure industrial edge gateway
System architecture and proposal development for an industrial gateway connecting field equipment, edge computing and secure communications.
Control & acquisition RTL
Digital interface and control-logic design for data acquisition, motor-control pipelines and inverter modulation.
Data-acquisition interface
16-channel bipolar ADC acquisition interface
Digital interface work for acquiring and organising measurements from a 16-channel bipolar analogue-to-digital conversion system.
Digital-to-analogue control
8-channel SPI DAC controller
Serial peripheral interface control for an eight-channel digital-to-analogue output system.
Motor-control datapath
Pipelined field-oriented motor controller
Pipelined control work covering Clarke and Park coordinate transforms, dual PI current regulation with anti-windup, and inverse Park transformation.
Inverter modulation
Centre-aligned three-phase space-vector PWM generator
Design work on centre-aligned three-phase space-vector pulse-width modulation (SVPWM) for inverter control.
Inverter gate-signal control
Gate-drive dead-time and fault protection
Gate-signal timing and dead-time insertion, with a one-cycle fault-trip design objective.
Around the work
A window into
my GitHub.
Explore public repositories
Explore my original public repositories and their latest updates on GitHub.
GitHub is contacted only when you choose to load this section.
Opportunities & collaboration
Discuss a role, collaboration
or engineering challenge.
Connect with me about engineering roles, research collaboration, technical reviews and project support.
Let’s start a conversation