W-02PUBLIC / EVIDENCE-CONTROLLEDREV 2026.08.24
SSWork
W-02RESTRICTED / AVIAT

Ethernet packet processing on AMD Kria KR260

AXI4 processing-system to programmable-logic co-design for Ethernet packet processing.

← Work ledger

Problem

The internship project concerned Layer-2 VLAN switching on a Zynq UltraScale+ SoC platform.

My contribution

The public record is limited to the certificate facts and the general hardware concepts exercised during the internship. It does not describe Aviat Networks implementation detail.

ARCHITECTURE / PUBLIC VIEW

System boundary

Public platform context for Kria KR260 workGeneric public platform context showing Ethernet input, processing-system boundary, AXI integration boundary and programmable logic. It is not the Aviat Networks implementation.ETHERNETPROCESSINGSYSTEMAXI / PS-PLBOUNDARYPL CONTEXT

This diagram shows only generic AMD platform boundaries. It is intentionally not the engagement architecture.

Implementation detail from this engagement is the property of Aviat Networks and is not published here.

VERIFICATION / LIMIT

What the record proves

The internship certificate establishes the organisation, duration and project title. No engagement-specific performance number, register map, implementation decision or internal validation artifact is published.

EVIDENCE
  • Aviat Networks internship certificate dated 13 Mar 2026 — privately held
  • Public AMD Zynq UltraScale+ / Kria platform context
  • Engagement repository and measurements not published
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