SS-00PUBLIC / EVIDENCE-CONTROLLEDREV 2026.08.24
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POSITION / 11.0168°NSCOPE / HARDWARE

Sundaram S S

SiliconDesign &IP Architecture

Deputy Head – Design ProcessZepto Logic Technologies · Coimbatore

Architecture · hardware · accelerators · NoC · integration interface · interconnection

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PUBLIC CAPABILITY FIELD / click a node to probe
Hardware architecture fieldInteractive conceptual map connecting architecture, interconnect, accelerators, security and verification. It describes public capability areas, not a confidential employer design. 01 / ARCHITECTUREspecification · partitioning 02 / INTERCONNECTAXI · NoC · boundaries 03 / ACCELERATORSdatapath organisation 04 / SECURITYbounded hardware enforcement 05 / VERIFICATIONclaim ↔ artifact
PROBE / 01Architecture before implementation.

I define the contract, partition and interface boundaries before implementation detail is allowed to dominate the design.

THESIS EVIDENCE / OWNER-CLEARED ACADEMIC RECORD

One quantified record. No decorative counters.

Figures below are owner-cleared thesis results. Tool-version/date metadata is not invented; the underlying artifact ledger is being normalized separately.

RULE SET17hardware-evaluated rules
LUT9.1%device utilisation
RULE8 nsevaluation latency
PARSE43–67 nsheader parsing latency
VALIDATION550k+captured Ethernet frames
ARP100%at 30k+ packets/s
Open evidence record W-01
WORK / PUBLIC RECORDS

Evidence is ranked by disclosure strength.

W-01FULLLayer-2 Ethernet security firewall in hardwareZynq-7000 · thesis→ W-02RESTRICTEDEthernet packet processing on AMD Kria KR260Aviat Networks · public scope only→ W-03SIMULATEDAXI4 master protocol verification environmentUVM · verification→ W-04IMPLEMENTEDTechnical documentation architectureengineering governance→
Open complete work ledger →
METHOD / THREE PRINCIPLES

How I decide before I design.

01

Architecture before implementation.

My output is definition, not volume. A specification that is right costs a fraction of the RTL that is wrong. I work at the layer where a programme is still cheap to change.

02

Claim only what the evidence supports.

Technical honesty is a design discipline. A result is useful only when its scope, method and limits survive scrutiny.

03

Reuse is an architectural decision.

Shared datapaths, configurable arithmetic and clean ready/valid boundaries are design choices, not shortcuts.

RESEARCH / PUBLIC RECORD

Four publications. Hardware positioning stays explicit.

IEEE · 2026Entropy-Driven FPGA-CPU Co-Designed SDN Defence for Resilient Edge NetworksDOI ↗ Springer · 2025Enhancing Sustainability in Industrial Workspaces: A Smart Approach to CO₂ Reduction and Environmental FootprintDOI ↗
Publication record →