RESEARCH / PUBLICATION RECORD

Published work, separated from current research direction.

Four public records are listed with author order and DOI where available. Summaries are original restatements, not copied abstracts.

P-01 / IEEE

Entropy-Driven FPGA-CPU Co-Designed SDN Defence for Resilient Edge Networks

Saritakumar N · Sundaram S S · Anusuya K. V.

2025 International Conference on Intelligent Innovations in Engineering and Technology · IEEE · published 19 Feb 2026

A simulation-backed RTL study of an FPGA-side streaming entropy monitor using AXI-Stream data movement and AXI4-Lite control/status. Hardware/ARM integration is not claimed by this record.

10.1109/ICIIET65921.2025.11379003 ↗

P-02 / SPRINGER

Enhancing Sustainability in Industrial Workspaces: A Smart Approach to CO₂ Reduction and Environmental Footprint

S. S. Sundaram · P. L. Sivaprabha Sri · R. Venkateswari

Smart System for Integrated Computing and Communication · Springer · pp. 455–467 · 2025

A conference chapter on reducing environmental impact in industrial workspaces through monitored and controlled building systems.

10.1007/978-3-031-99939-0_35 ↗

P-03 / SPRINGER

Sustainable Building Management Through AI, ML, and Advanced Technologies

Vinoth Kumar · Sundaram · Sivaprabha Sri · Sri Varshini

Studies in Systems, Decision and Control, Vol. 564 · Springer · pp. 153–164 · 2024

A book chapter examining intelligent building-management approaches for efficiency and sustainability. It is retained as publication history, not as an AI/ML engineering capability claim.

10.1007/978-3-031-70399-7_11 ↗

P-04 / IJARIIE

An Alternative Approach for Dynamic Wireless Charging

Eswar R M · Pooja M · Sundaram S S · Sivaprabha Sri P L

International Journal of Advance Research and Innovative Ideas in Education · Vol. 9, No. 1 · pp. 1579–1585 · 2023

An undergraduate publication exploring an alternative dynamic wireless-charging arrangement for electric vehicles.

Journal record ↗

DIRECTION

Where the hardware work is heading

hardware security · side-channel-resistant architecture · cryptographic accelerator design · deterministic hardware network defence

Research direction is not presented as completed capability.Doctoral status is intentionally not stated.

TRAINING

Maven Silicon — VLSI SoC Design (Verilog)

PSG College of Technology / Qualcomm — System-Level Verification Workshop

IIT Bombay — Spoken Tutorial

HONOURS

Anna University TN-CEETA Postgraduate Merit Scholar — 88.275 percentile

PSG Achievers Award

Mahatma Gandhi Merit Scholar

MEMBERSHIP

VLSI Society of India — Tamil Nadu Chapter

International Association of Engineers (IAENG)