Simulation · SystemVerilog / UVM
AXI4 master verification environment
Separating stimulus, observation, checking, and coverage to make protocol behaviour easier to verify.
01 / The challenge
Engineering objective
Protocol verification needs independent observation and checking so a transaction can be judged against expected behaviour, beyond visual waveform inspection.
02 / My contribution
My role & contribution
I constructed an AXI4 master-side verification environment around sequencer, driver, monitor, scoreboard, and coverage responsibilities.
03 / The approach
Technical approach
- Generate transactions through a sequence and sequencer.
- Drive the design-under-test interface through a dedicated driver.
- Observe activity independently with a monitor.
- Feed observations to checking and coverage components.
04 / The outcome
Results & project status
A structured simulation environment with separate stimulus and checking paths for AXI4 master-side protocol behaviour.
Results cover simulation-based verification of AXI4 master-side protocol behaviour.